This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to single-electron transistors and fabrication methods therefor.
Single-electron Transistor (SET) devices and fabrication methods are being widely investigated for high density and/or high performance microelectronic devices. As is well known to those having skill in the art, single-electron transistors use single-electron nanoelectronics that can operate based on the flow of single-electrons through nanometer-sized particles, also referred to as nanoparticles, nanoclusters or quantum dots. Although a single-electron transistor can be similar in general principle to a conventional Field Effect Transistor (FET), such as a conventional Metal Oxide Semiconductor FET (MOSFET), in a single-electron transistor, transfer of electrons may take place based on the tunneling of single-electrons through the nanoparticles. Single-electron transistors are described, for example, in U.S. Pat. Nos. 5,420,746; 5,646,420; 5,844,834; 6,057,556 and 6,159,620, and in publications by the present inventor Brousseau, III et al., entitled pH-Gated Single-Electron Tunneling in Chemically Modified Gold Nanoclusters, Journal of the American Chemical Society, Vol. 120, No. 30, 1998, pp. 7645-7646, and by Feldheim et al., entitled Self-Assembly of Single Electron Transistors and Related Devices, Chemical Society Reviews, Vol. 27, 1998, pp. 1-12, and in a publication by Klein et al., entitled A Single-Electron Transistor Made From a Cadmium Selenide Nanocrystal, Nature, 1997, pp. 699-701, the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
A major breakthrough in single-electron transistor technology is described in U.S. patent application Ser. No. 09/376,695, entitled Sensing Devices Using Chemically-Gated Single Electron Transistors, by Daniel L. Feldheim and the present inventor Louis C. Brousseau, III, also published as International Publication No. WO 01/13432 A1, the disclosures of which are hereby incorporated herein by reference in their entirety as if set fully herein. Described therein is a chemically-gated single-electron transistor that can be adapted for use as a chemical or biological sensor. Embodiments of these chemically-gated single-electron transistors include source and drain electrodes on a substrate and a nanoparticle between the source and drain electrodes, that has a spatial dimension of a magnitude of approximately 12 nm or less. An analyte-specific binding agent is disposed on a surface of the nanoparticle. A binding event occurring between a target analyte and the binding agent causes a detectable change in the characteristics of the single-electron transistor.
Notwithstanding these and other configurations of single-electron transistors, including chemically-gated single-electron transistors, it may be difficult to fabricate these devices using conventional photolithography that is employed to fabricate microelectronic devices. In particular, in order to provide quantum mechanical effects with nanoparticles, it may be desirable to provide spacing between the source and drain electrodes of a single-electron transistor that is less than about 20 nm, or less than about 12 nm or about 10 nm. It may be difficult, however, to provide these spacings using conventional lithography at low cost and/or with acceptable device yields.
Embodiments of the present invention provide single-electron transistors and manufacturing methods therefor, in which first and second electrodes and an insulating layer therebetween are provided on a substrate. The insulating layer has a thickness that defines a spacing between the first and second electrodes. At least one nanoparticle is provided on the insulating layer. Accordingly, a desired spacing between the first and second electrodes may be obtained without the need for high resolution photolithography.
Embodiments of the present invention may stem from a realization that thin film insulating layers, such as insulating layers that are about 10 nm thick, can be fabricated using conventional microelectronic fabrication techniques, such as chemical vapor deposition, whereas it may be difficult to photolithographically define a region in a layer that is, for example, 10 nm wide. According to embodiments of the invention, single-electron structures and fabrication methods may be provided that allow the thickness of an insulating layer between first and second electrodes to determine spacing between the first and second electrodes. Accordingly, single-electron transistor devices may be fabricated using conventional microelectronic techniques with the potential of low cost and/or high yields.
Single-electron transistors according to embodiments of the present invention comprise a substrate including a face. A first electrode extends from the face, and includes a first electrode end and a sidewall. In some embodiments, the first electrode end is remote from the face, and the sidewall extends between the face and the first electrode. The first electrode may be regarded as a post, tower, mesa, tip, pyramid or cone electrode. An insulating layer is provided on the sidewall, the insulating layer including an insulating layer end that is remote from the face. A second electrode is provided on the insulating layer opposite the sidewall. The second electrode includes a second electrode end. At least one nanoparticle is provided on the insulating layer end. In some embodiments, the insulating layer is less than about 20 nm thick. In other embodiments, the insulating layer is less than about 12 nm thick, and in other embodiments the insulating layer is about 10 nm thick.
In some embodiments of the present invention, the insulating layer end is a continuous insulating layer end that surrounds the sidewall. In other embodiments, the second electrode end is a continuous second electrode end that surrounds the continuous insulating layer end. In yet other embodiments, the continuous insulating layer end and the continuous second electrode end form first and second rings, respectively, that surround the first electrode end. In still other embodiments, the first and second rings are circular, elliptical and/or polygonal first and second rings. In yet other embodiments, the first electrode insulating end and the second electrode insulating end are coplanar.
In some embodiments, the at least one nanoparticle on the insulating layer end comprises a plurality of nanoparticles on the insulating layer end, wherein the first electrode end and the second electrode end are free of nanoparticles thereon. In other embodiments, nanoparticles also are included on the first electrode end and/or on the second electrode end.
In yet other embodiments, a self-assembled monolayer is provided on the insulating layer end, wherein the at least one nanoparticle is on the self-assembled monolayer, opposite the insulating layer end. In still other embodiments, the self-assembled monolayer also is provided on the first electrode end and/or on the second electrode end.
Embodiments of the invention as described above may be used to form an electrically-gated single-electron transistor, wherein a gate electrode is provided on the at least one nanoparticle opposite the insulating layer end. In other embodiments, a chemically-gated single-electron transistor may be provided by providing an analyte-specific binding agent on a surface of the at least one nanoparticle. Moreover, in any of the above embodiments, arrays of single-electron transistors may be formed on the substrate, wherein an array of first electrodes may be provided on the substrate, portions of a single insulating layer may provide the insulating layers on the array of first electrodes and portions of a single conductive layer may provide an array of second electrodes on the array of first electrodes.
Single-electron transistors may be fabricated, according to embodiments of the present invention, by forming a first electrode on a substrate, conformally forming an insulating layer on at least a portion of the first electrode and conformally forming a second electrode on at least a portion of the insulating layer opposite the first electrode. At least one nanoparticle is placed on the insulating layer, between the first electrode and the second electrode.
In some method embodiments, the first electrode is formed by forming a mask region on the substrate and anisotropically etching the substrate with the mask region thereon, to form the first electrode on the first substrate having a first electrode end, with the mask region on the first electrode end. In some embodiments, the insulator is conformally formed on the first electrode, except for the first electrode end that has the mask region thereon and the second electrode is conformally formed on the insulating layer, except for the first electrode end that has the mask region thereon. Moreover, in other embodiments, the mask region is removed from the first electrode end prior to placing the nanoparticle. The nanoparticle is placed on the insulating layer adjacent the first electrode end.
In other method embodiments, the second electrode and the insulating layer are removed from the first electrode end prior to placing the at least one nanoparticle on the insulating layer. The second electrode and the insulating layer may be removed from the first electrode end by forming a recessed layer on the substrate, such that the first electrode end, the insulating layer on the first electrode end and the second electrode on the first electrode end protrude from the recessed layer. The first electrode, the insulating layer on the first electrode end and the second electrode layer on the first electrode end that protrude from the recessed layer are then planarized. Accordingly, the thickness of the insulating layer may determine the spacing between the first and second electrodes, to thereby allow a single-electron transistor to be fabricated using conventional microelectronic processing steps, while allowing high performance and/or high yields.